Performance Analysis of the 8-way P6 Based Systems

The performance of a NUMA system is defined by the type and number of microprocessors within a node as well as the interconnection network within and between nodes. Pipelining the transactions accessing system and internode buses as well as local and remote memory modules improves utilization of system resources. However, analysis of pipelined systems have proven to be difficult to obtain. This paper presents an analytical methodology and numerical results for P6 based pipelined systems. The analysis was done for different ratios between bus and microprocessor frequencies with a wide variation of the I/O and cache coherency and internode traffic. The main attention was paid to analysis of contention in accessing pipelined shared resources (memory modules, system and internode buses) which limits the number of processors effectively used in a system. A good agreement between analytical and simulation results in obtaining system performance estimates is shown at the final section of the paper. Key-words: NUMA, performance, node, microprocessor, memory, cache, processor/memory bus, clock rate 1 P6 is the code name for the Intel Pentium family of microprocessors